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<h1><a title="按下即可以搜尋參考至本頁的資料" rel="nofollow" href="http://www.google.com/cse?cx=004774160799092323420:6-ff2s0o6yi&amp;q=%22auto-complete-verilog.el%22">auto-complete-verilog.el</a></h1></div><div class="wrapper"><div class="content browse"><p class="download"><a href="download/auto-complete-verilog.el">Download</a></p><pre class="code"><span class="linecomment">;;; auto-complete-verilog.el --- </span>

<span class="linecomment">;; Copyright 2009 Yen-Chin,Lee</span>
<span class="linecomment">;;</span>
<span class="linecomment">;; Author: Yen-Chin,Lee</span>
<span class="linecomment">;; Version: $Id: auto-complete-verilog.el,v 0.0 2009/04/25 17:26:34 coldnew Exp $</span>
<span class="linecomment">;; Keywords: </span>
<span class="linecomment">;; X-URL: not distributed yet</span>

<span class="linecomment">;; This program is free software; you can redistribute it and/or modify</span>
<span class="linecomment">;; it under the terms of the GNU General Public License as published by</span>
<span class="linecomment">;; the Free Software Foundation; either version 2, or (at your option)</span>
<span class="linecomment">;; any later version.</span>
<span class="linecomment">;;</span>
<span class="linecomment">;; This program is distributed in the hope that it will be useful,</span>
<span class="linecomment">;; but WITHOUT ANY WARRANTY; without even the implied warranty of</span>
<span class="linecomment">;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</span>
<span class="linecomment">;; GNU General Public License for more details.</span>
<span class="linecomment">;;</span>
<span class="linecomment">;; You should have received a copy of the GNU General Public License</span>
<span class="linecomment">;; along with this program; if not, write to the Free Software</span>
<span class="linecomment">;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.</span>

<span class="linecomment">;;; Commentary:</span>

<span class="linecomment">;; </span>

<span class="linecomment">;; Put this file into your load-path and the following into your ~/.emacs:</span>
<span class="linecomment">;;   (require 'auto-complete-verilog)</span>

<span class="linecomment">;;; Code:</span>

(provide 'auto-complete-verilog)
(eval-when-compile
  (require 'cl))
(require 'auto-complete)

<span class="linecomment">;;;;##########################################################################</span>
<span class="linecomment">;;;;  User Options, Variables</span>
<span class="linecomment">;;;;##########################################################################</span>

(defface ac-verilog-candidate-face
  '((t (:background "<span class="quote">snow3</span>" :foreground "<span class="quote">black</span>")))
  "<span class="quote">Face for verilog candidate</span>")

(defface ac-verilog-selection-face
  '((t (:background "<span class="quote">SlateBlue3</span>" :foreground "<span class="quote">black</span>")))
  "<span class="quote">Face for the verilog selected candidate.</span>")


(defvar ac-verilog-sources
  '(verilog-keywords))

(ac-define-dictionary-source
 verilog-keywords '(
<span class="linecomment">;; verilog-type-font-keywords</span>
	     "<span class="quote">and</span>" "<span class="quote">bit</span>" "<span class="quote">buf</span>" "<span class="quote">bufif0</span>" "<span class="quote">bufif1</span>" "<span class="quote">cmos</span>" "<span class="quote">defparam</span>"
	     "<span class="quote">event</span>" "<span class="quote">genvar</span>" "<span class="quote">inout</span>" "<span class="quote">input</span>" "<span class="quote">integer</span>" "<span class="quote">localparam</span>"
	     "<span class="quote">logic</span>" "<span class="quote">mailbox</span>" "<span class="quote">nand</span>" "<span class="quote">nmos</span>" "<span class="quote">not</span>" "<span class="quote">notif0</span>" "<span class="quote">notif1</span>" "<span class="quote">or</span>"
	     "<span class="quote">output</span>" "<span class="quote">parameter</span>" "<span class="quote">pmos</span>" "<span class="quote">pull0</span>" "<span class="quote">pull1</span>" "<span class="quote">pullup</span>"
	     "<span class="quote">rcmos</span>" "<span class="quote">real</span>" "<span class="quote">realtime</span>" "<span class="quote">reg</span>" "<span class="quote">rnmos</span>" "<span class="quote">rpmos</span>" "<span class="quote">rtran</span>"
	     "<span class="quote">rtranif0</span>" "<span class="quote">rtranif1</span>" "<span class="quote">semaphore</span>" "<span class="quote">signed</span>" "<span class="quote">struct</span>" "<span class="quote">supply</span>"
	     "<span class="quote">supply0</span>" "<span class="quote">supply1</span>" "<span class="quote">time</span>" "<span class="quote">tran</span>" "<span class="quote">tranif0</span>" "<span class="quote">tranif1</span>"
	     "<span class="quote">tri</span>" "<span class="quote">tri0</span>" "<span class="quote">tri1</span>" "<span class="quote">triand</span>" "<span class="quote">trior</span>" "<span class="quote">trireg</span>" "<span class="quote">typedef</span>"
	     "<span class="quote">uwire</span>" "<span class="quote">vectored</span>" "<span class="quote">wand</span>" "<span class="quote">wire</span>" "<span class="quote">wor</span>" "<span class="quote">xnor</span>" "<span class="quote">xor</span>"
<span class="linecomment">;; verilog-p1800-keywords</span>
         "<span class="quote">alias</span>" "<span class="quote">assert</span>" "<span class="quote">assume</span>" "<span class="quote">automatic</span>" "<span class="quote">before</span>" "<span class="quote">bind</span>"
	     "<span class="quote">bins</span>" "<span class="quote">binsof</span>" "<span class="quote">break</span>" "<span class="quote">byte</span>" "<span class="quote">cell</span>" "<span class="quote">chandle</span>" "<span class="quote">class</span>"
	     "<span class="quote">clocking</span>" "<span class="quote">config</span>" "<span class="quote">const</span>" "<span class="quote">constraint</span>" "<span class="quote">context</span>" "<span class="quote">continue</span>"
	     "<span class="quote">cover</span>" "<span class="quote">covergroup</span>" "<span class="quote">coverpoint</span>" "<span class="quote">cross</span>" "<span class="quote">deassign</span>" "<span class="quote">design</span>"
	     "<span class="quote">dist</span>" "<span class="quote">do</span>" "<span class="quote">edge</span>" "<span class="quote">endclass</span>" "<span class="quote">endclocking</span>" "<span class="quote">endconfig</span>"
	     "<span class="quote">endgroup</span>" "<span class="quote">endprogram</span>" "<span class="quote">endproperty</span>" "<span class="quote">endsequence</span>" "<span class="quote">enum</span>"
	     "<span class="quote">expect</span>" "<span class="quote">export</span>" "<span class="quote">extends</span>" "<span class="quote">extern</span>" "<span class="quote">first_match</span>" "<span class="quote">foreach</span>"
	     "<span class="quote">forkjoin</span>" "<span class="quote">genvar</span>" "<span class="quote">highz0</span>" "<span class="quote">highz1</span>" "<span class="quote">ifnone</span>" "<span class="quote">ignore_bins</span>"
	     "<span class="quote">illegal_bins</span>" "<span class="quote">import</span>" "<span class="quote">incdir</span>" "<span class="quote">include</span>" "<span class="quote">inside</span>" "<span class="quote">instance</span>"
	     "<span class="quote">int</span>" "<span class="quote">intersect</span>" "<span class="quote">large</span>" "<span class="quote">liblist</span>" "<span class="quote">library</span>" "<span class="quote">local</span>" "<span class="quote">longint</span>"
	     "<span class="quote">matches</span>" "<span class="quote">medium</span>" "<span class="quote">modport</span>" "<span class="quote">new</span>" "<span class="quote">noshowcancelled</span>" "<span class="quote">null</span>"
	     "<span class="quote">packed</span>" "<span class="quote">program</span>" "<span class="quote">property</span>" "<span class="quote">protected</span>" "<span class="quote">pull0</span>" "<span class="quote">pull1</span>"
	     "<span class="quote">pulsestyle_onevent</span>" "<span class="quote">pulsestyle_ondetect</span>" "<span class="quote">pure</span>" "<span class="quote">rand</span>" "<span class="quote">randc</span>"
	     "<span class="quote">randcase</span>" "<span class="quote">randsequence</span>" "<span class="quote">ref</span>" "<span class="quote">release</span>" "<span class="quote">return</span>" "<span class="quote">scalared</span>"
	     "<span class="quote">sequence</span>" "<span class="quote">shortint</span>" "<span class="quote">shortreal</span>" "<span class="quote">showcancelled</span>" "<span class="quote">small</span>" "<span class="quote">solve</span>"
	     "<span class="quote">specparam</span>" "<span class="quote">static</span>" "<span class="quote">string</span>" "<span class="quote">strong0</span>" "<span class="quote">strong1</span>" "<span class="quote">struct</span>"
	     "<span class="quote">super</span>" "<span class="quote">tagged</span>" "<span class="quote">this</span>" "<span class="quote">throughout</span>" "<span class="quote">timeprecision</span>" "<span class="quote">timeunit</span>"
	     "<span class="quote">type</span>" "<span class="quote">union</span>" "<span class="quote">unsigned</span>" "<span class="quote">use</span>" "<span class="quote">var</span>" "<span class="quote">virtual</span>" "<span class="quote">void</span>"
	     "<span class="quote">wait_order</span>" "<span class="quote">weak0</span>" "<span class="quote">weak1</span>" "<span class="quote">wildcard</span>" "<span class="quote">with</span>" "<span class="quote">within</span>"
<span class="linecomment">;; verilog-ams-keywords</span>
         "<span class="quote">above</span>" "<span class="quote">abs</span>" "<span class="quote">absdelay</span>" "<span class="quote">acos</span>" "<span class="quote">acosh</span>" "<span class="quote">ac_stim</span>"
	     "<span class="quote">aliasparam</span>" "<span class="quote">analog</span>" "<span class="quote">analysis</span>" "<span class="quote">asin</span>" "<span class="quote">asinh</span>" "<span class="quote">atan</span>" "<span class="quote">atan2</span>" "<span class="quote">atanh</span>"
	     "<span class="quote">branch</span>" "<span class="quote">ceil</span>" "<span class="quote">connectmodule</span>" "<span class="quote">connectrules</span>" "<span class="quote">cos</span>" "<span class="quote">cosh</span>" "<span class="quote">ddt</span>"
	     "<span class="quote">ddx</span>" "<span class="quote">discipline</span>" "<span class="quote">driver_update</span>" "<span class="quote">enddiscipline</span>" "<span class="quote">endconnectrules</span>"
	     "<span class="quote">endnature</span>" "<span class="quote">endparamset</span>" "<span class="quote">exclude</span>" "<span class="quote">exp</span>" "<span class="quote">final_step</span>" "<span class="quote">flicker_noise</span>"
	     "<span class="quote">floor</span>" "<span class="quote">flow</span>" "<span class="quote">from</span>" "<span class="quote">ground</span>" "<span class="quote">hypot</span>" "<span class="quote">idt</span>" "<span class="quote">idtmod</span>" "<span class="quote">inf</span>"
	     "<span class="quote">initial_step</span>" "<span class="quote">laplace_nd</span>" "<span class="quote">laplace_np</span>" "<span class="quote">laplace_zd</span>" "<span class="quote">laplace_zp</span>"
	     "<span class="quote">last_crossing</span>" "<span class="quote">limexp</span>" "<span class="quote">ln</span>" "<span class="quote">log</span>" "<span class="quote">max</span>" "<span class="quote">min</span>" "<span class="quote">nature</span>"
	     "<span class="quote">net_resolution</span>" "<span class="quote">noise_table</span>" "<span class="quote">paramset</span>" "<span class="quote">potential</span>" "<span class="quote">pow</span>" "<span class="quote">sin</span>"
	     "<span class="quote">sinh</span>" "<span class="quote">slew</span>" "<span class="quote">sqrt</span>" "<span class="quote">tan</span>" "<span class="quote">tanh</span>" "<span class="quote">timer</span>" "<span class="quote">transition</span>" "<span class="quote">white_noise</span>"
	     "<span class="quote">wreal</span>" "<span class="quote">zi_nd</span>" "<span class="quote">zi_np</span>" "<span class="quote">zi_zd</span>"
<span class="linecomment">;; verilog-font-keywords</span>
         "<span class="quote">assign</span>" "<span class="quote">case</span>" "<span class="quote">casex</span>" "<span class="quote">casez</span>" "<span class="quote">randcase</span>" "<span class="quote">deassign</span>"
	     "<span class="quote">default</span>" "<span class="quote">disable</span>" "<span class="quote">else</span>" "<span class="quote">endcase</span>" "<span class="quote">endfunction</span>"
	     "<span class="quote">endgenerate</span>" "<span class="quote">endinterface</span>" "<span class="quote">endmodule</span>" "<span class="quote">endprimitive</span>"
	     "<span class="quote">endspecify</span>" "<span class="quote">endtable</span>" "<span class="quote">endtask</span>" "<span class="quote">final</span>" "<span class="quote">for</span>" "<span class="quote">force</span>" "<span class="quote">return</span>" "<span class="quote">break</span>"
	     "<span class="quote">continue</span>" "<span class="quote">forever</span>" "<span class="quote">fork</span>" "<span class="quote">function</span>" "<span class="quote">generate</span>" "<span class="quote">if</span>" "<span class="quote">iff</span>" "<span class="quote">initial</span>"
	     "<span class="quote">interface</span>" "<span class="quote">join</span>" "<span class="quote">join_any</span>" "<span class="quote">join_none</span>" "<span class="quote">macromodule</span>" "<span class="quote">module</span>" "<span class="quote">negedge</span>"
	     "<span class="quote">package</span>" "<span class="quote">endpackage</span>" "<span class="quote">always</span>" "<span class="quote">always_comb</span>" "<span class="quote">always_ff</span>"
	     "<span class="quote">always_latch</span>" "<span class="quote">posedge</span>" "<span class="quote">primitive</span>" "<span class="quote">priority</span>" "<span class="quote">release</span>"
	     "<span class="quote">repeat</span>" "<span class="quote">specify</span>" "<span class="quote">table</span>" "<span class="quote">task</span>" "<span class="quote">unique</span>" "<span class="quote">wait</span>" "<span class="quote">while</span>"
	     "<span class="quote">class</span>" "<span class="quote">program</span>" "<span class="quote">endclass</span>" "<span class="quote">endprogram</span>"
<span class="linecomment">;; verilog-type-keywords</span>
         "<span class="quote">and</span>" "<span class="quote">buf</span>" "<span class="quote">bufif0</span>" "<span class="quote">bufif1</span>" "<span class="quote">cmos</span>" "<span class="quote">defparam</span>" "<span class="quote">inout</span>" "<span class="quote">input</span>"
         "<span class="quote">integer</span>" "<span class="quote">localparam</span>" "<span class="quote">logic</span>" "<span class="quote">mailbox</span>" "<span class="quote">nand</span>" "<span class="quote">nmos</span>" "<span class="quote">nor</span>" "<span class="quote">not</span>" "<span class="quote">notif0</span>"
         "<span class="quote">notif1</span>" "<span class="quote">or</span>" "<span class="quote">output</span>" "<span class="quote">parameter</span>" "<span class="quote">pmos</span>" "<span class="quote">pull0</span>" "<span class="quote">pull1</span>" "<span class="quote">pullup</span>"
         "<span class="quote">rcmos</span>" "<span class="quote">real</span>" "<span class="quote">realtime</span>" "<span class="quote">reg</span>" "<span class="quote">rnmos</span>" "<span class="quote">rpmos</span>" "<span class="quote">rtran</span>" "<span class="quote">rtranif0</span>"
         "<span class="quote">rtranif1</span>" "<span class="quote">semaphore</span>" "<span class="quote">time</span>" "<span class="quote">tran</span>" "<span class="quote">tranif0</span>" "<span class="quote">tranif1</span>" "<span class="quote">tri</span>" "<span class="quote">tri0</span>" "<span class="quote">tri1</span>"
         "<span class="quote">triand</span>" "<span class="quote">trior</span>" "<span class="quote">trireg</span>" "<span class="quote">wand</span>" "<span class="quote">wire</span>" "<span class="quote">wor</span>" "<span class="quote">xnor</span>" "<span class="quote">xor</span>"
<span class="linecomment">;; verilog-cpp-keywords</span>
         "<span class="quote">module</span>" "<span class="quote">macromodule</span>" "<span class="quote">primitive</span>" "<span class="quote">timescale</span>" "<span class="quote">define</span>" 
         "<span class="quote">ifdef</span>" "<span class="quote">ifndef</span>" "<span class="quote">else</span>" "<span class="quote">endif</span>"
<span class="linecomment">;; verilog-defun-keywords</span>
         "<span class="quote">always</span>" "<span class="quote">always_comb</span>" "<span class="quote">always_ff</span>" "<span class="quote">always_latch</span>" "<span class="quote">assign</span>"
         "<span class="quote">begin</span>" "<span class="quote">end</span>" "<span class="quote">generate</span>" "<span class="quote">endgenerate</span>" "<span class="quote">module</span>" "<span class="quote">endmodule</span>"
         "<span class="quote">specify</span>" "<span class="quote">endspecify</span>" "<span class="quote">function</span>" "<span class="quote">endfunction</span>" "<span class="quote">initial</span>" "<span class="quote">final</span>"
<span class="linecomment">;; verilog-block-keywords</span>
         "<span class="quote">begin</span>" "<span class="quote">break</span>" "<span class="quote">case</span>" "<span class="quote">continue</span>" "<span class="quote">else</span>" "<span class="quote">end</span>" "<span class="quote">endfunction</span>"
         "<span class="quote">endgenerate</span>" "<span class="quote">endinterface</span>" "<span class="quote">endpackage</span>" "<span class="quote">endspecify</span>" "<span class="quote">endtask</span>"
         "<span class="quote">for</span>" "<span class="quote">fork</span>" "<span class="quote">if</span>" "<span class="quote">join</span>" "<span class="quote">join_any</span>" "<span class="quote">join_none</span>" "<span class="quote">repeat</span>" "<span class="quote">return</span>"
         "<span class="quote">while</span>"
<span class="linecomment">;; verilog-tf-keywords</span>
         "<span class="quote">begin</span>" "<span class="quote">break</span>" "<span class="quote">fork</span>" "<span class="quote">join</span>" "<span class="quote">join_any</span>" "<span class="quote">join_none</span>" "<span class="quote">case</span>" 
         "<span class="quote">end</span>" "<span class="quote">endtask</span>" "<span class="quote">endfunction</span>" "<span class="quote">if</span>" "<span class="quote">else</span>" "<span class="quote">for</span>" "<span class="quote">while</span>" "<span class="quote">repeat</span>"
<span class="linecomment">;; verilog-case-keywords</span>
         "<span class="quote">begin</span>" "<span class="quote">fork</span>" "<span class="quote">join</span>" "<span class="quote">join_any</span>" "<span class="quote">join_none</span>" "<span class="quote">case</span>" "<span class="quote">end</span>" 
         "<span class="quote">endcase</span>" "<span class="quote">if</span>" "<span class="quote">else</span>" "<span class="quote">for</span>" "<span class="quote">repeat</span>"
<span class="linecomment">;verilog-separator-keywords</span>
         "<span class="quote">else</span>" "<span class="quote">then</span>" "<span class="quote">begin</span>"
))

(defvar ac-source-verilog
      '((candidates . (lambda ()
                        (all-completions ac-target verilog-keywords)))
        (candidate-face . ac-verilog-candidate-face)
        (selection-face . ac-verilog-selection-face)
        (requires . 3))
      "<span class="quote">Source for verilog.</span>")

<span class="linecomment">;;; auto-complete-verilog.el ends here</span></span></pre></div><div class="wrapper close"></div></div><div class="footer"><hr /><span class="gotobar bar"><a class="local" href="http://www.emacswiki.org/emacs/%e7%b6%b2%e7%ab%99%e5%9c%b0%e5%9c%96">網站地圖</a> <a class="local" href="http://www.emacswiki.org/emacs/%e6%9c%80%e8%bf%91%e6%9b%b4%e6%96%b0">最近更新</a> <a class="local" href="http://www.emacswiki.org/emacs/News">News</a> <a class="local" href="http://www.emacswiki.org/emacs/ElispArea">ElispArea</a> <a class="local" href="http://www.emacswiki.org/emacs/%e6%95%99%e5%af%bc">教导</a> </span><span class="translation bar"><br />  <a class="translation new" rel="nofollow" href="http://www.emacswiki.org/emacs?action=translate;id=auto-complete-verilog.el;missing=de_en_es_fr_it_ja_ko_pt_ru_se_zh">Add Translation</a></span><span class="edit bar"><br /> <a class="edit" accesskey="e" title="按此即可編輯此頁面" rel="nofollow" href="http://www.emacswiki.org/emacs?action=edit;id=auto-complete-verilog.el">編輯本頁</a> <a class="history" rel="nofollow" href="http://www.emacswiki.org/emacs?action=history;id=auto-complete-verilog.el">參閱其他版本</a> <a class="admin" rel="nofollow" href="http://www.emacswiki.org/emacs?action=admin;id=auto-complete-verilog.el">管理 Oddmuse</a></span><span class="time"><br /> 最後編輯於 2009-04-26 08:52 UTC 由 <a class="author" title="自 220-134-36-21.HINET-IP.hinet.net" href="http://www.emacswiki.org/emacs/coldnew">coldnew</a> <a class="diff" rel="nofollow" href="http://www.emacswiki.org/emacs?action=browse;diff=2;id=auto-complete-verilog.el">(比較差異)</a></span><div style="float:right; margin-left:1ex;">
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